A ferroelectric memory is a non-volatile voltage-driven semiconductor memory device and preferably provides high operational speed, low electric power consumption and non-volatility of information in that the information held therein is retained even when the electric power is turned off. Ferroelectric memories are already used in IC cards and other portable electronic apparatuses.
In ferroelectric memories, a ferroelectric film constituting a ferroelectric capacitor easily undergoes reduction by the reducing ambient used generally in semiconductor processes; however, such a reduction of the ferroelectric film raises a problem of ferroelectric degradation. Thus, various proposals have been made for suppressing reduction of the ferroelectric film, including Japanese Laid-Open Patent Application 2005-57103.
FIG. 1 is a cross-sectional diagram illustrating the construction of a ferroelectric memory device 10 called a stacked type device according to a related art.
Referring to FIG. 1, the ferroelectric memory device 10 is a so-called 1T1C device and includes two memory cell transistors formed in a device region 11A defined on a silicon substrate 11 by a device isolation region 11I such that the two memory cell transistors share a bit line.
More specifically, there is formed an n-type well in the silicon substrate 11 as the device region 11A, wherein there are formed, on the device region 11A, a first MOS transistor having a polysilicon gate electrode 13A and a second MOS transistor having a polysilicon gate electrode 13B via respective gate insulation films 12A and 12B.
In the silicon substrate 11, there are formed LDD regions 11a and 11b of p−-type in correspondence to respective sidewalls of the gate electrode 13A, and there are further formed LDD regions 11c and 11d of p−-type in correspondence to respective sidewalls of the gate electrode 13B. Thereby, the first and second MOS transistors are formed commonly in the device region 11A, and thus, the same p-type diffusion region is used as the LDD region 11b and the LDD region 11c. 
On the polysilicon gate electrodes 13A and 13B, there are formed silicide layers 14A and 14B, respectively, and there are further formed sidewall insulation films on the sidewall surfaces of the polysilicon gate electrode 13A and on the sidewall surfaces of the polysilicon gate electrode 13B, respectively.
Furthermore, diffusion regions 11e and 11f of p+-type are formed in the silicon substrate 11 at respective outer sides of the sidewall insulation films of the gate electrode 13A, and diffusion regions 11g and 11h of p+-type are formed in the silicon substrate 11 at respective outer sides of the sidewall insulation films of the gate electrode 13B. Furthermore, diffusion regions 11f and 11g are formed by the same p+-type diffusion region.
Further, on the silicon substrate 11, there is formed an SiON film 15 so as to cover the gate electrode 13A including the silicide layer 14A and the sidewall insulation films of the gate electrode 13A and so as to cover the gate electrode 13B including the silicide layer 14B and the sidewall insulation films on the gate electrode 13B, and an interlayer insulation film 16 of SiO2 is formed on the SiON film 15. Further, contact holes 16A, 16B and 16C are formed in the interlayer insulation film 16 so as to expose the diffusion region 11e, the diffusion region 11f (the diffusion region 11g), and the diffusion region 11h, respectively, wherein via-plugs 17A, 17B and 17C of W (tungsten) are formed in the respective contact holes 16A, 16B and 16C via adhesive layers 17a, 17b and 17c, wherein each of the adhesive layers 17a, 17b and 17c is formed by lamination of a Ti film and a TiN film.
Further, on the interlayer insulation film 16, there is formed a first ferroelectric capacitor C1 in which a lower electrode 18A, a polycrystalline ferroelectric film 19A and an upper electrode 20A are stacked in contact with the tungsten plug 17A. Similarly, a second ferroelectric capacitor C2 is formed on the interlayer insulation film 16 by stacking of a lower electrode 18C, a polycrystalline ferroelectric film 19C and an upper electrode 20C in contact with the tungsten plug 17C.
Further, on the interlayer insulation film 16, there is formed a hydrogen barrier film 21 of Al2O3 so as to cover the ferroelectric capacitors C1 and C2, and a next interlayer insulation film 22 is formed further on the hydrogen barrier film 21.
On the interlayer insulation film 22, there is formed a next hydrogen barrier film 24 of Al2O3, and a further interlayer insulation film 25 is formed on the hydrogen barrier film 24.
Further, in the interlayer insulation film 25, there are formed a contact hole 25A exposing the upper electrode 20A of the ferroelectric capacitor C1, a contact hole 25B exposing the via-plug 17B, and a contact hole 25C exposing the upper electrode 20C of the ferroelectric capacitor C2, wherein the contact holes 25A-25C are formed respectively with tungsten plugs 23A, 23B and 23C via respective adhesion layers 23a, 23b and 23c formed by lamination of a Ti film and a TiN film.
Further, Al interconnection patterns 26A, 26B and 26C are formed on the interlayer insulation film 25 respectively in correspondence to the tungsten plugs 23A, 23B and 23C with a barrier metal film of the Ti/TiN layered structure.
With the ferroelectric memory of the construction of FIG. 1, the interlayer insulation film 22 covering the ferroelectric capacitors C1 and C2 are formed generally by a plasma CVD process that uses a source material of small water content such as TEOS. Further, the ferroelectric capacitors C1 and C2 are covered with the hydrogen barrier film 21. Even so, the problem caused by the hydrogen for the ferroelectric capacitors C1 and C2 associated with the interlayer insulation film is not completely resolved.
FIGS. 2A and 2B show a part of the fabrication process of the ferroelectric memory of FIG. 1.
Referring to FIG. 2A, the interlayer insulation film 22 is planarized by a CMP process after formation thereof, and an Al2O3 film 24 is formed on such a planarized interlayer insulation film 22 in FIG. 2B. In order to suppress the degradation of the ferroelectric capacitors C1 and C2 by reduction, it is preferable to reduce the film thickness of the interlayer insulation film 22 as much as possible in the CMP (chemical mechanical polishing) of foregoing FIG. 2A.
On the other hand, it is preferable, with the ferroelectric capacitors C1 and C2, to form the upper electrodes 20A and 20C with a conductive oxide, particularly with an IrO2 film or a RuO2 film such that there is caused no degradation of ferroelectricity in the ferroelectric capacitor by way of activation of hydrogen, even in the case hydrogen has caused invasion thereinto through the hydrogen barrier film 21. However, an IrO2 film or a RuO2 film has poor resistance against CMP, and the upper electrode 20A or 20C cannot stop the polishing process in such a case in which polishing has reached the ferroelectric capacitor C1 or C2.
Under these situations, it has been practiced conventionally to form the interlayer insulation film 22 to have a large thickness and a tolerance D of 300 nm or more is secured over the ferroelectric capacitor.
However, when the film thickness of the interlayer insulation film 22 is increased like this, there arises a problem, apart from the problem explained previously that water in the interlayer insulation film 22 causes deterioration of characteristics of the ferroelectric capacitors C1 and C2, that there is caused a significant increase of distance from the substrate 11 to the top surface of the interlayer insulation film 22, and hence to the top surface of the interlayer insulation film 25, while this leads to the problem that it is difficult to form a contact hole extending from a pattern on the interlayer insulation film 25 to the substrate 11.